View 74LVT573_4584965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

74LVT573
3.3 V octal D-type transparent latch; (3-state)
Rev. 04 -- 15 September 2008 Product data sheet
1. General description
The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
2. Features
I I I I I I I I I I I Inputs and outputs arranged for easy interfacing to microprocessors 3-state outputs for bus interfacing Common output enable control TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up reset Power-up 3-state Latch-up protection N JESD78 class II exceeds 500 mA I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from -40 C to +85 C
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVT573D 74LVT573DB 74LVT573PW 74LVT573BQ -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C SO20 SSOP20 TSSOP20 DHVQFN20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm Version SOT163-1 SOT339-1 SOT360-1 Type number
plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm
4. Functional diagram
11 1 1 2 3 4 5 6 7 8 9 OE D0 D1 D2 D3 D4 D5 D6 D7 LE 11
mna807
C1 EN1
2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 4 5 6 7 8 9 3
1D
19 18 17 16 15 14 13 12
mna808
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
2 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig 3.
Logic diagram
5. Pinning information
5.1 Pinning
74LVT573 74LVTH573
terminal 1 index area 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 GND(1) GND 10 LE 11 13 Q6 12 Q7 OE 2 3 4 5 6 7 8 9 1 D0 D1 OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE
001aah713
74LVT573 74LVTH573
D2 D3 D4 D5 D6 D7
GND 10
001aah712
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4.
Pin configuration for SO20, and (T)SSOP20
Fig 5.
Pin configuration for DHVQFN20
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
3 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
5.2 Pin description
Table 2. Symbol OE D0 to D7 GND LE Q0 to Q7 VCC Pin description Pin 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 Description output enable input (active LOW) data input ground (0 V) latch enable (active HIGH) data output supply voltage
6. Functional description
6.1 Function table
Table 3. Function table [1] Control OE L L L H Control LE H L X Input Dn L H l h Hold Disable outputs
[1]
Operating mode Load and read register enable Latch and read register
Internal register Output Qn L H L H NC NC L H L H NC Z
X X
H = HIGH voltage level; L = LOW voltage level; = HIGH-to-LOW latch enable transition; h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition; l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition; Z = high-impedance OFF-state; NC = no change; X = don't care.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO Parameter supply voltage input voltage output voltage input clamping current output clamping current output current output in OFF-state or HIGH-state VI < 0 V VO < 0 V output in LOW-state output in HIGH-state
[1] [1]
Conditions
Min -0.5 -0.5 -0.5 -
Max +4.6 +7.0 +7.0 -50 -50 128 -64
Unit V V V mA mA mA mA
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
4 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
Table 4. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Tstg Tj Ptot
[1] [2] [3]
Parameter storage temperature junction temperature total power dissipation
Conditions
[2]
Min -65 -
Max +150 150 500
Unit C C mW
Tamb = -40 C to +85 C
[3]
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5. Symbol VCC VI VIH VIL IOH IOL Tamb t/V Recommended operating conditions Parameter supply voltage input voltage HIGH-level input voltage LOW-level input voltage HIGH-level output current LOW-level output current current duty cycle 50 %; fi 1 kHz ambient temperature input transition rise and fall rate in free air outputs enabled Conditions Min 2.7 0 2.0 -40 Typ Max 3.6 5.5 0.8 -32 32 64 +85 10 Unit V V V V mA mA mA C ns/V
9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIK VOH input clamping voltage HIGH-level output voltage Conditions VCC = 2.7 V; IIK = -18 mA VCC = 2.7 V to 3.6 V; IOH = -100 A VCC = 2.7 V; IOH = -8 mA VCC = 3.0 V; IOH = -32 mA VOL LOW-level output voltage VCC = 2.7 V; IOL = 100 A VCC = 2.7 V; IOL = 24 mA VCC = 3.0 V IOL = 16 mA VCC = 3.0 V IOL = 32 mA VCC = 3.0 V IOL = 64 mA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = GND or VCC
[2]
Tamb = -40 C to +85 C Min -1.2 Typ[1] -0.9 Max 0.2 0.5 0.4 0.5 0.55 0.55
Unit V V V V V V V V V V
VCC - 0.2 VCC - 0.1 2.4 2.0 2.5 2.2 0.1 0.3 0.25 0.3 0.4 0.13
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
5 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter II input leakage current Conditions all input pins; VCC = 0 V or 3.6 V; VI = 5.5 V control pins; VCC = 3.6 V; VCC or GND data pins VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V IOFF IBHL IBHH IBHHO IBHLO ILO IO(pu/pd) IOZ power-off leakage current bus hold LOW current bus hold HIGH current bus hold HIGH overdrive current bus hold LOW overdrive current output leakage current power-up/power-down output current OFF-state output current VCC = 0 V; VI or VO = 0 V to 4.5 V Dn input; VCC = 3 V; VI = 0.8 V Dn input; VCC = 3 V; VI = 2.0 V Dn input; VCC = 0 V to 3.6 V Dn input; VI = 3.6 V Qn output HIGH when VO = 5.5 V and VCC = 3.0 V VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE = don't care VCC = 3.6 V; VI = VIH or VIL output HIGH: VO = 3.0 V output LOW: VO = 0.5 V ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A outputs HIGH outputs LOW outputs disabled ICC additional supply current per input pin; VCC = 3 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND VI = 0 V or 3.0 V outputs disabled; VO = 0 V or 3.0 V
[6] [7] [5] [4] [4] [3]
Tamb = -40 C to +85 C Min -5 75 -500 Typ[1] 1 0.1 0.1 -1 1 150 -150 60 1 Max 10 1 1 100 -75 500 125 100
Unit
A A A A A A A A A A A
-5
1 -1
5 -
A A
-
0.13 3 0.13 0.1
0.19 12 0.19 0.2
mA mA mA mA
CI CO
[1] [2] [3] [4] [5] [6] [7]
input capacitance output capacitance
-
4 8
-
pF pF
Typical values are measured at VCC = 3.3 V and Tamb = 25 C. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only. ICC is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
6 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
10. Dynamic characteristics
Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Figure 11. Symbol Parameter tPLH LOW to HIGH propagation delay Conditions LE to Qn; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V Dn to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPHL HIGH to LOW propagation delay LE to Qn; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V Dn to Qn; see Figure 7 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPZH OFF-state to HIGH propagation delay OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPZL OFF-state to LOW propagation delay OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPHZ HIGH to OFF-state propagation delay OE to Qn; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 2.7 V tPLZ LOW to OFF-state propagation delay OE to Qn; see Figure 9 VCC = 3.0 V to 3.6 V VCC = 2.7 V tsu set-up time Dn to LE; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 2.7 V th hold time Dn to LE; see Figure 10 VCC = 3.0 V to 3.6 V VCC = 2.7 V tW pulse width LE input HIGH; see Figure 6 VCC = 3.0 V to 3.6 V VCC = 2.7 V
[1] [2] [3] [4] Typical values are at VCC = 3.3 V and Tamb = 25 C. tsu is the same as tsu(L) and tsu(H). th is the same as th(L) and th(H). tW is the same as tWL and tWH.
(c) NXP B.V. 2008. All rights reserved.
Tamb = -40 C to +85 C Unit Min 1.6 1.0 2.5 1.0 1.0 1.3 2.0 1.5 [2]
Typ 3.5 2.5 4.3 2.7 2.8 3.3 3.7 3.0 -
Max 5.6 6.3 4.2 4.7 6.5 7.2 4.3 5.2 5.1 6.2 5.5 6.6 5.7 6.7 4.6 5.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.7 0.6
[3]
1.6 1.8
[4]
3.3 3.3
74LVT573_4
Product data sheet
Rev. 04 -- 15 September 2008
7 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
11. Waveforms
VI LE input 0V tWH tPHL VOH Qn output VOL VM
001aai743
VM Dn input tWL tPLH
VI VM 0V tPHL VOH Qn output VOL VM
001aai742
tPLH
Measurement points are given in Table 8.
Measurement points are given in Table 8.
Fig 6.
Propagation delays latch enable input (LE) to output (Qn), and latch enable (LE) pulse width
VI
Fig 7.
Propagation delay data input (Dn) to output (Qn)
VI
OE input 0V
VM tPZH
VM tPHZ
OE input 0V
VM tPZL
VM tPLZ VM VX
001aai746
VOH Qn output 0V VM
3.0 V VY Qn output VOL
001aai745
Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.
Measurement points are given in Table 8.
Fig 8.
Output enable time to HIGH-state and output disable time from HIGH-state
VI Dn input 0V VM
Fig 9.
Output enable time to LOW-state and output disable time from LOW-state
th(H) tsu(L) VI LE input 0V VM tsu(H)
th(L)
001aai744
Measurement points are given in Table 8. Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs Table 8. Input VM 1.5 V
74LVT573_4
Measurement points Output VM 1.5 V VX VOL + 0.3 V VY VOH - 0.3 V
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
8 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VEXT VCC PULSE GENERATOR VI DUT
RT CL RL RL
VO
001aae235
Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times.
Fig 11. Test circuitry for switching times Table 9. Input VI 2.7 V fi 10 MHz tW 500 ns tr, tf 2.5 ns Test data Load CL 50 pF RL 500 VEXT tPHZ, tPZH GND tPLZ, tPZL 6V tPLH, tPHL open
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
9 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 12. Package outline SOT163-1 (SO20)
74LVT573_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
10 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 10 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 13. Package outline SOT339-1 (SSOP20)
74LVT573_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
11 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 14. Package outline SOT360-1 (TSSOP20)
74LVT573_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
12 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 9 vMCAB wM C y1 C
C y
1 Eh 20
10 e 11
19 Dh 0
12 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 15. Package outline SOT764-1 (DHVQFN20)
74LVT573_4 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
13 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
13. Abbreviations
Table 10. Acronym BiCMOS DUT ESD HBM MM TTL Abbreviations Description Bipolar Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date 20080915 Data sheet status Product data sheet Change notice Supersedes 74LVT573_3 Document ID 74LVT573_4 Modifications:
* * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3 "Ordering information" and Section 12 "Package outline": DGHVQFN20 package added. Table 4 "Limiting values" Tj and Ptot added. Table 6 "Static characteristics" VRST changed to VOL; IHOLD changed to IBHL, IBHH, IBHHO and IBHLO; ICCH, ICCL and ICCZ changed to ICC; Ci changed to CI and COUT changed to CO. Table 7 "Dynamic characteristics" tsu(H) and tsu(L) changed to tsu; th(H) and th(L) changed to th and tW(H) and tW(L) changed to tW. Product data sheet Product specification 74LVT573_2 -
74LVT573_3 74LVT573_2
20011217 19980219
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
14 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74LVT573_4
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 -- 15 September 2008
15 of 16
NXP Semiconductors
74LVT573
3.3 V octal D-type transparent latch; (3-state)
17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 September 2008 Document identifier: 74LVT573_4

▲Up To Search▲

Price & Availability of 74LVT573

	To Download 74LVT573 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .